This is the top level view: Since nothing can be seen from this I have included a .pdf version. Underneath is an image of how the Comparators are hooked up to the resistor string, and how the NAND2's with the inverting inputs convert the string of 0's and 1's output by the comparator into a single bit code. For example if the input voltage is half of the reference, then the bottom half of the comparators would output a zero and the top half would output ones. This is then converted into a 255-bit bus which is now a string of 1's except for one lone zero where the transition occurs, the location of this zero is then encoded into an 8-bit binary number by the ENC256 block. It's operation is described in the "Larger Digital Blocks" section.
Blown up below is the rest of the circuitry, this schematic includes some "test equipement." This includes an ahdl model of a sample-and-hold and a DAC to test the output of the A/D. The circuit behaves in the same way as described by the specification document at the top of the page.
| # of Cells Used | # of Transistors | Total |
| 255 | 30 | 7650 |
Larger Digital Blocks
| Name | Description | Daugther Cells | Qty | # of Tran. | # of Instances |
| 256 to 8 Encoder | Converts the outputs of the NAND's to an 8-bit binary value | ENC16 OR16_4 | 17 1 | 1718 | 1 |
| 16 to 4 Encoder | Checks a 16-bit bus for a 1 to 0 transition | NAND4 INV OR2 NOR4 AND2 | 6 3 3 2 1 | 94 | 17 |
| LSB OR | ORs the LSB outputs from the 16 ENC16 blocks | OR4 | 20 | 120 | 1 |
| Output Registers | Description | Daugther Cells | Qty | # of Tran. | 1 |
Standard Cells:
| Name | Description | Daugther Cells | Qty | # of Tran. | # of Instances |
| AND2 | Min. Dimension 2-input AND | NAND2 INV | 2 2 | 6 | 17 |
| BUF | Min. Dimension Buffer | INV | 2 | 4 | ??? |
| BUFx3 | Buffer with 3x output | INV INVx3 | 1 1 | 8 | ??? |
| DFF | Min. Dimension D flip-flop | INV TG | 5 4 | 18 | 8 |
| INV | Min. Dimension Inverter | none | - | 2 | 91 |
| INVx3 | Inverter 3x output | none | - | 6 | ??? |
| NAND2 | Min. Dimension 2-input NAND | none | - | 4 | ??? |
| NAND2_1INV | Min. Dimension 2-input NAND with inverted B input | NAND2 INV | 1 1 | 6 | ??? |
| NAND4 | Min. Dimension 4-input NAND | none | - | 8 | ??? |
| NOR2 | Min. Dimension 2-input NOR | none | - | 4 | ??? |
| NOR4 | Min. Dimension 4input NOR | none | - | 8 | ??? |
| OR2 | Min. Dimension 2-input OR | NOR2 INV | 1 1 | 6 | ??? |
| OR4 | Min. Dimension 4-input OR | none | NOR41 1 | 10 | ??? |
| TG | Min. Dimension Transmission gate | none | - | 2 | ??? |
L indicates a low logic level
H indicates a high logic level
R indicates a rising edge
F indicates a falling edge
What I tried to do was to measure the propagation delay with every combination of inputs that caused a change at the output. Then I took the slowest cases and put those numbers into the verilog models. Also slightly pesimistic was the load of a NAND4 at the output of the cell being tested, but this helps account to interconnect parasitics.
Total transistor count: 10,642
Final thoughts:- A better comparator might have been chosen. This is a classic design which doesn't lend itself to quick power downs and power ups.
- The digital logic might be modified in some way as to force the LSB's from each of the Encoders to propagate through at the same speed, this would reduce the jitter at the output. If this is completely eliminated, then the output latches won't be needed.
- The digital logic might be redesigned to have symetrical rise and fall times, this is related to the above point.
- It also has yet to be determined if the jitter at the output of the ENC16 block is due to temporary bubble errors, in which case I might use a 3 input NAND with terminals B and C in a NOT configuration, and I would look for two 0's followed by a 1.
- Complete the top level simulations and measure INL, DNL, and THD
- Perform and LVS of the Top Level schematic (the cells themselves are done, that includes every cell layout in this webpage)
- Simulate some worst case scenarios on the comparator, and measure how this will affect the maximum clocking speed.
Questions? Comments? Email me: iknausz@lsil.com